Conventionally, there is a high demand for a solid-state imaging element capable of reading out pixel signals at high speed. Furthermore, due to the recent expansion of applications used in small terminals such as smartphones and wearable devices, there is also a high demand for suppressing power consumption of solid-state imaging elements. For example, while a conventional method of achieving high speed is by increasing the number of parallel stages of the column parallel analog-digital (AD) converter as described above, this method increases power consumption in proportion to the increase in the number of parallel stages of the column parallel AD converter, making it difficult to improve the power efficiency (=speed/power). In other words, the power consumption increases with the speeding up, while the speed is reduced with the reduction of the power consumption.
As a countermeasure, there is a proposed technique (refer to Patent Document 1) that performs AD conversion operation of a pixel signal output from a pixel connected via another vertical signal line in parallel with reset operation or signal transfer operation of a pixel connected via a part of vertical signal lines so as to reduce power consumption by alternately repeating the above operations.